Qualitative and Quantitative Analysis of Timed SDL Speci cations
نویسندگان
چکیده
Timed SDL (TSDL) is a modiied version of SDL designed for the examination of qualitative and quantitative system aspects within one model description. Because realistic communication protocols tend to be very large a program package was developed, which transforms a TSDL model into an internal representation of an equivalent Finite State Machine (FSM). This FSM representation can be eeciently analyzed by algorithms for qualitative and quantitative protocol analysis. In particular algorithms for partial state space exploration have shown to be very suitable. One of these algorithms is described in detail and is slightly improved. It is shown, that this kind of analysis leads to reasonable results, even for large models.
منابع مشابه
Veri cation of SDL Speci cations on the Basis of Stream Semantics
This paper presents a new approach to the formal veri cation of SDL speci cations SDL is given de notational semantics based on the concepts of streams and stream processing functions in the formal framework of Focus The formalization of SDL revealed some aspects of SDL which are handled un precisely in the Z e g the concept of time and gives a solution to them The formal semantics is the start...
متن کاملTransforming SDL Diagrams into a Complete Visual Representation
| We investigate a translation of SDL diagrams into the complete visual representation of Pictorial Janus (PJ) programs in order to analyze the speci cation by visual debugging and animation. We additionally introduce timing concepts to PJ (Timed PJ) for a mapping of the SDL timing statements. The concepts transforming SDL interaction and process diagrams into Timed PJ are outlined by an exampl...
متن کاملVHDL generation from SDL speci cations
The aim of this paper is to present an approach that allows the generation of VHDL from system level speci cations in SDL. Our approach overcome the main known problem encountered by previous work which is the communication between di erent processes. We allow SDL communication to be translated into VHDL for synthesis. This is made possible by the use of an intermediate form that support a powe...
متن کاملTimed Extensions for SDL
In this paper we propose some extensions necessary to enable the speci-cation and description language SDL to become an appropriate formalism for the design of real-time and embedded systems. The extensions we envisage concern both roles of SDL: First, in order to make SDL a real-time speciication language, allowing to correctly simulate and verify real-time speciications, we propose a set of a...
متن کاملEarly performance prediction of SDL/MSC specified systems by automated synthetic code generation
We present a new approach for early performance prediction based on MSC speci ed systems in the context of SDL Our approach is integrated into existing design methodologies as proposed by commercial tool vendors where communication software is fully speci ed in SDL and the nal implementation is derived from there Obviously the structure of the SDL speci cation will in uence the performance of t...
متن کامل